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ThesisItem Open Access Blind equalization of bipolar 2-PAM and 4-QAM signals using non-linear autoregressive exogenous input neural system(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-08) Singh, Vipra; Mathur, SanjayThis thesis presents a study on the blind equalization of Bipolar 2-PAM and 4-QAM signals using Non-Linear Autoregressive Exogenous Input (NARX) neural system. The thesis can be divided into two parts, the first part involves the theoretical issues about the blind equalization and neural equalizers, the second part addresses the problem of software implementation. The thesis begins with some basic concepts and theories of the channel equalization, which are fundamentals for designing blind equalizers, and then introduces blind equalization concept. Next presented in the thesis is the neural network architecture that is suitable for blind equalization. Its stability and convergence properties are analyzed in the thesis. Also, the thesis proposes a blind equalization model that combines the concept of decision-feedback equalizer and the NARX neural networks. Simulations with 2-PAM and 4-QAM signals have been carried out to test the performances of the proposed model. The second part of the thesis presents a software equalizer design which has been simulated. Based on the results from the simulation, the performance of the neural equalizer is discussed. Finally, some suggestions for further work are included at the end of the thesis.ThesisItem Open Access Controllable notched edge tapered rectangular patch antenna using U-slot line feed and DGS for UWB applications(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-08) Sharma, Sunil; ParasAntenna is an extremely indispensible part of wireless communication systems. As the requirements of wireless devices increasing day by day like Bluetooth devices, radio frequency devices and size of such devices decreasing accordingly. To meet the requirement of small size devices, antenna need to be compact and single antenna can be used for several wireless applications, without affecting the antenna parameters. Therefore the concept of ultra-wideband is used. The defected ground structure and slotting is used to enhance the performance of antenna. Proposed antenna is designed in the substrate size of 35×30 with height of 1.6mm. FR-4 epoxy substrate having permittivity of 4.4 and loss tangent of .02 is used. Ground size is reduced to obtain monopole antenna and slots are cut on both patch as well as ground plane to improve the performance of antenna in terms of bandwidth and gain. Proposed antenna is simulated using Ansoft HFSS software, fabricated in PCB designing machine and tested using VNA. Proposed antenna resonates in 3.1-14.45GHz band with notched frequency bands from 3.31-3.6GHz (WiMAX) and 4.4-5.8GHz (WLAN) with the bandwidth of 11.35 GHz having gain above 2.17dB and efficiency 80-90% throughout the entire frequency range. Proposed antenna has applications in UWB frequency range with no interference for WiMAX and WLAN band in wireless communication.ThesisItem Open Access Compact broadband microstrip antenna with DGS for wireless applications(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-08) Pant, Bharat; Gangwar, R.P.S.With the rapid growth of wireless communications in recent years, users need multiple frequency bands at the same time to access different services such as voice video and data. Therefore, it has become to have compact microstrip antenna (MSA) with a wide band to avoid employing multiple antennas to fulfil requirement of the users. The MSA is a revolution in the field of wireless applications due to its low cost, ease of installation, performance and low profile structure which make it a high quality contender. for many communication equipment. The main objective of this proposed work is to develop a compact broadband microstrip antenna with DGS for wireless applications in the frequency range of 2-7 GHz. The proposed antenna is designed using TLM model and is simulated and optimized using HFSSv.15 with a centre frequency of 4GHz. Proposed antenna is used to operate at the frequency range of 2.73-6.50 GHz in wireless applications like WiMAX (3.6 GHz), Hi-LAN (5.15-5.35 GHz), WLAN IEEE802a (5.2 GHZ), and DSRC for a car to car communication (5.850-5.925 GHz). A 6-6.50 GHz might be used for future 5G communication and other application as CCTV, Camera and Cmax. The proposed antenna is fabricated on a FR4 substrate having thickness 1.6 mm and loss tangent of 0.02. The fabricated antenna has dimensions 32×22×1.6 mm3which makes it compact in nature. The parameters in terms of reflection coefficient and VSWR for the proposed antenna (fabricated) are measured and compared with the simulated ones, which show good agreement. The proposed antenna is also compared with the earlier designed antennas. The measured broad bandwidth with reflection coefficient below -10 dB is found to be 4500 MHz in the frequency range from 2.70- 7.2 GHz. Simulated peak gain of 5.22 dBi and radiation efficiency of 90-98% for the proposed antenna in the frequency range from 2.73 - 6.50 GHz are observed. The proposed antenna has a stable radiation pattern in both E and H planes.ThesisItem Open Access A triangular patch monopole antenna with DGS ground having CSRR based controllable notch characteristics for UWB applications(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-08) Upreti, Mitesh; ParasMonopole configuration and DGS in antenna is used to achieve a high bandwidthUWB antenna (3.1-10.6 GHz) with acceptable gain. The main concern of UWB antenna is that they are sensitive towards electromagnetic interferences with existing narrowband wireless communication systems, so it is necessary to design antennas with multiband filtering characteristics to avoid interferences. Therefore, it is necessary to design the UWB antenna with band notched characteristics to reduce the complexity and make cost effective systems. The proposed work consists of a triangular patch antenna monopole antenna having dual band notch characteristics for the UWB applications. The size of the antenna is 24×28×1.6 mm3.Dielectric substrate used is FR4 epoxy having dielectric constant εr = 4.4 and loss tangenttan 𝛿 = 0.02. The variant of proposed antenna is also designed to confirm the controllability feature of CSRR notch. The proposed antenna resonates in the UWB range from 3.1 to 11 GHz and peak gain of 7 dB at 10.84 GHz (Proposed Antenna). The dual notch band characteristics due to inverted U slot and CSRR is obtained from 4.9 to 5.36 GHz to 6.1 to 6.78 GHz for the proposed antenna. The variant of proposed antenna shows the shifting of CSRR notch from 6.1 to 6.78 GHz to 7.2 to 7.8 GHz by reducing the size of CSRR by 0.5 mm. The geometric parameters of inverted U slot & CSRRs are chosen to eliminate interference with the WLAN/Future mobile communications or X band.ThesisItem Open Access Design of low power and high speed sense amplifier based Flip-Flop in 90nm CMOS technology(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-08) Pandey, Kailash; Tomar, AbhishekWith the increasing processor speed demand of peripheral devices of high speed and low power consumption has grown. Power consumption in the circuits can be reduced by decreasing capacitance at the high impedance nodes along with the reduction in the number of transistors. So flip-flops are used which is the main building block in designing the digital circuits that creates a larger impact on circuits speed and power consumption. Performance of flip-flop also determines the performance of the whole synchronous circuit. sense amplifier based flip-flops which are a type of master-slave flip-flop are designed having a simple design of slave latch, less clock skew and nearly zero set-up time. The proposed designs achieve a reduction in power by the use of the method of conditional precharging. The slave latch designs minimize the latency of the circuit. The designs show improvement in PDP. These design works for different ranges of voltages which exhibits the robustness and suitability of the circuits. Cadence Virtuoso 90nm CMOS technology tool is used for the simulations. In comparison to various SAFF studied the proposed designs show more than 26.27% and 31.72% improvement in delay and power respectively.ThesisItem Open Access Design of low power inverter based OTA in FinFET technology(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-02) Mohit Kumar; Sharma, K.K.OTA performance analysed by following four different analysis on SPICE tool First DC analysis of proposed circuit is done on input sweep from -0.7 to 0.7 to understand the output current behaviour and finding proper operating point. The following parameter has been calculated as – Output current swing from -125μV to 125μV, differential mode transconductance 215.29 μS at IDS = 23 μA and total power consumption at Z=50Ω is 234μW. VG1 and VG4 terminal voltage can be used to tune the transconducatance value. There is no need of extra regulated on chip supply voltage. Second, Frequency response analysis is performed to calculate differential mode gain , common mode gain, unity gain bandwidth, phase margin, CMRR, PSRR. Achieved open loop gain of the circuit is 52dB , unity gain bandwidth is 1Ghz at CL = 0.1pF , phase margin is 80˚,PSRR+ obtained 52.007dB, PSRR- obtained 52.012dB, CMRR obtained 49.5dB. Positive slew rate and negative slew rate values are 1.034 v/ns and 0.83 v/ns respectively In proposed circuit noise analysis has been done at load Z=50Ω. Proposed circuit suffer with total input noise value of 1.08μV/√Hz and total output noise calculated to be 6.43nV/√Hz .ThesisItem Open Access Simulation study of dual edge triggered static flip flop in FinFET technology(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-02) Dinesh Kumar; Sharma, K.K.The current very large scale integration technology (VLSI) based on bulk MOSFETs has approached the scaling limits, due to increased leakage and short channel effects (SCEs). Fin field effect transistors (FinFETs) is a promising alternative for addressing the challenges posed by continued scaling and allowing further scaling. Fabrication of FinFETs is compatible with that of conventional CMOS, thus making possible the very rapid deployment to manufacturing. Flip-flop is main building block in digital circuits that have large impact on circuit speed and power consumption. Performance of flip-flop determines the performance of whole synchronous circuit. Switching activity of a circuit node is a main concern to reduce dynamic power. Dynamic power is directly proportional to switching activity. Switching activity can vary according to input data thereby for different input data pattern different power dissipation can occur. Dual edge triggering is an effective way to reduce the power consumption, it can reduce switching activity for same data throughout. In this thesis, different existing dual edge triggered static flip-flop have been studied and their performances have been evaluated using CMOS and FinFET technology. All these circuits have been simulated with the help of HSPICE simulator. 32nm CMOS technology is used for MOSFET based flip-flop and Berkeley predictive technology model (BPTM) is used for 32nm CMOS and FinFET based dual edge triggered flipflops. Simulation results of CMOS based flip-flops are then compared with the simulation result of FinFET based flip-flops. Parameters considered for the comparison are power consumption, delay and power delay product. With the help of simulation results it is observed that FinFET improved all the parameters of dual edge triggered flip-flops.ThesisItem Open Access Design of low power high resolution time-to-digital converter in 45 nm CMOS technology(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2019-01) Gurmail Singh; Tomar, AbhishekIncrease in the speed of processor demands peripheral devices that can simultaneously operate at high speed while consuming very little power. Power consumption can be reduced by decreasing the effective capacitance at the high impedance nodes of the circuit along with reduction in the number of transistors. Proposed time-to digital converter (TDC) design uses 1024 stages. High number of stages are incorporated to achieve a very good resolution. Circuit is designed by using less number of transistors in order to reduce the power consumption as well as increase the speed of the circuit. Proposed TDC can be used as a phase/frequency detector in Phase Locked-Loop (PLL). In comparison to pseudo differential delay line based TDC and proposed TDC, speed and resolution is improved by more than 19% and 37.5% respectively. PDP has improved. HSPICE tool using 45nm CMOS technology is used for simulationThesisItem Open Access Design of high speed and low power clock controlled flip-flop in 90 nm CMOS technology(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2018-07) Joshi, Vijay; Tomar, AbhishekIncreasing processor speed demands peripheral devices of high speed and low power consumption. Power consumption can be reduced by decreasing capacitance of the circuit. Proposed clock blocked flip-flop (CBFF) design uses only 11 transistors and blocks data path after a fixed time. This time can be controlled by delay of inverter used. As data path is open only for small time, power dissipation decreases. Proposed CBFF can be used for large serial data as data loading is limited to two transistors in the design. Low clock load is achieved as only two clocked transistors are used. As there is no need of refreshing circuit when data is changed, PDP is improved. Proposed flip-flop only uses static ratio insensitive differential latch (SRIS), thus achieving complementary output nodes with reduced loading. Cadence Virtuoso tool is used for simulations. In comparison to sense amplifier based flip-flop (SAFF), modified SAFF, Strollo’s flip-flop and self-blocking flip-flop (SBFF), speed and PDP is improved by more than 20 and 15% respectively.
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