Simulation study of dual edge triggered static flip flop in FinFET technology
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Date
2019-02
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
The current very large scale integration technology (VLSI) based on bulk MOSFETs has approached the scaling limits, due to increased leakage and short channel effects (SCEs). Fin field effect transistors (FinFETs) is a promising alternative for addressing the challenges posed by continued scaling and allowing further scaling. Fabrication of FinFETs is compatible with that of conventional CMOS, thus making possible the very rapid deployment to manufacturing. Flip-flop is main building block in digital circuits that have large impact on circuit speed and power consumption. Performance of flip-flop determines the performance of whole synchronous circuit. Switching activity of a circuit node is a main concern to reduce dynamic power. Dynamic power is directly proportional to switching activity. Switching activity can vary according to input data thereby for different input data pattern different power dissipation can occur. Dual edge triggering is an effective way to reduce the power consumption, it can reduce switching activity for same data throughout. In this thesis, different existing dual edge triggered static flip-flop have been studied and their performances have been evaluated using CMOS and FinFET technology. All these circuits have been simulated with the help of HSPICE simulator. 32nm CMOS technology is used for MOSFET based flip-flop and Berkeley predictive technology model (BPTM) is used for 32nm CMOS and FinFET based dual edge triggered flipflops. Simulation results of CMOS based flip-flops are then compared with the simulation result of FinFET based flip-flops. Parameters considered for the comparison are power consumption, delay and power delay product. With the help of simulation results it is observed that FinFET improved all the parameters of dual edge triggered flip-flops.
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