Design of high speed and low power clock controlled flip-flop in 90 nm CMOS technology
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Date
2018-07
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
Increasing processor speed demands peripheral devices of high speed and low power consumption. Power consumption can be reduced by decreasing capacitance of the circuit. Proposed clock blocked flip-flop (CBFF) design uses only 11 transistors and blocks data path after a fixed time. This time can be controlled by delay of inverter used. As data path is open only for small time, power dissipation decreases. Proposed CBFF can be used for large serial data as data loading is limited to two transistors in the design. Low clock load is achieved as only two clocked transistors are used. As there is no need of refreshing circuit when data is changed, PDP is improved. Proposed flip-flop only uses static ratio insensitive differential latch (SRIS), thus achieving complementary output nodes with reduced loading. Cadence Virtuoso tool is used for simulations. In comparison to sense amplifier based flip-flop (SAFF), modified SAFF, Strollo’s flip-flop and self-blocking flip-flop (SBFF), speed and PDP is improved by more than 20 and 15% respectively.
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