Design of second order sigma delta modulator using preamplifier latch based comparator in 180 nm CMOS technology
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Date
2015-07
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
Sigma Delta Modulator (SDM) is achieving attention due to its low cost, high resolution, high signal to noise ratio etc in analog to digital converter. In SDM, the oversampling frequency is used to achieve high resolution. Also, noise shaping is inherently done to reduce noise power. The noise power in the design of SDM can be further reduced by increasing the order of the SDM. In this thesis, a second order continuous time, upto 50 kHz, SDM is designed with 1.8 V supply voltage in 180nm CMOS technology. The blocks used in SDM like integrator, subtractor and gain stages are implemented using Operational Amplifier (Op-amp) which is designed in cascade topology with miller capacitance techniques to optimize the phase margin and gain. The designed Op-amp has gain of 59.302 dB, phase margin of 59.2° and Gain Bandwidth (GBW) of 114.6 MHz. Integrator has -20 dB/decade slope for 11.12 kHz to 10.62 MHz which decides the sampling frequency of 3.2MHz. The preamplifier based latch comparator is used as a final stage of SDM. The designed preamplifier has 18.167 dB gain and 779.77 MHz 3-dB frequency which amplify low amplitude signal. The designed comparator is able to differentiate the 50uV signal and the sampling frequency is 64 MHz. The simulation is done in Cadence Virtuoso tool.With an input signal of 50 kHz and 3.2MHz clock frequency, the SNDR is 59.2 dB and power dissipation is 8.7mW of the SDM.
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