Design & performance analysis of trigate junctionless 22nm TFET
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Date
2020-12
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
Nowadays, Nano scale devices are in demand due to their higher packing density and high performance in microelectronics circuits. These nano-scale devices, suffer with short channel effects including DIBL, Sub-threshold slope, small Ion/Ioff ratio, large leakage current etc. To overcome these short channel effects, we have proposed a 22 nm Dual Material Gate Tri-gate Junctionless FinFET. The gate of this device is made up of two material Tungston and Silver, with work function of 5.2 eV and 4.74 eV, respectively. The proposed DM DG JL FinFET is simulated using software Visual TCAD. The Effect of Dual Material Gate work function Difference on Electrical Characteristics like ION/IOFF, Subthreshold slope, DIBL is simulated. The simulation results of proposed device show subthreshold slope of 62.64mV/dec – 68.19mV/dec, ION/IOFF ratio of 5.49E+07- 3.898E9 and DIBL 18.6 mV/V-60.02mV/dec for a workfiunction deiffenece from 0.0eVto 0.8eV. The proposed devices due to three side gates have better control on charge carriers in the channel. Further, two metal gate improves carrier transport efficiency, reduce short channel
effects in term of DIBL, Subthreshold slope and improves ION/IOFF ratio. The reduction achieved is 5% - 23% in subthreshold slope and 67% - 85% in DIBL. The proposed device has low leakage current and is very useful for memory circuits.