Design of multiple loop architecture based ring oscillator in 0.18µm CMOS technology
| dc.contributor.advisor | Tomar, Abhishek | |
| dc.contributor.author | Goel, Ankit | |
| dc.date.accessioned | 2018-07-09T09:30:59Z | |
| dc.date.available | 2018-07-09T09:30:59Z | |
| dc.date.issued | 2016-07 | |
| dc.description.abstract | Phase noise, frequency tuning and power dissipation are the important parameter in designing any ring VCO with the contemporary sub-micron technologies. Phase noise improvement is still not up to the mark so that ring oscillator can be used in RF applications. Various designs had developed by using effecting topology for reducing power dissipation and phase noise. In this thesis, a novel design of ring VCO has been proposed and implemented in TMSC 0.18µm CMOS technology. The proposed novel design is compared with the earlier proposed design in different CMOS technology for phase noise, tunning range and power dissipation. The simulation is done using cadence EDA tool. The simulated result shows a phase noise of -107.56 dBc/Hz @ 1MHz offset from 2.6 GHz center frequency with a power consumption of 35mW. The layout is drawn and post layout simulation is done which verifies the pre layout results. To reduce phase noise and power dissipation, transistors in sub- feedback loop are operated in linear and cut off region and transistors in main loop of inverter are designed for fast switching with large voltage swing to minimize the switching current. The proposed schematic occupies an area of 48.28 x 38.89 µm2. | en_US |
| dc.identifier.uri | http://krishikosh.egranth.ac.in/handle/1/5810058508 | |
| dc.keywords | information technology, communication | en_US |
| dc.language.iso | en | en_US |
| dc.pages | 64 | en_US |
| dc.publisher | G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand) | en_US |
| dc.research.problem | Information Technology | en_US |
| dc.sub | Electrical Engineering | en_US |
| dc.subject | null | en_US |
| dc.theme | Electronics and Communication Engineering | en_US |
| dc.these.type | M.Tech | en_US |
| dc.title | Design of multiple loop architecture based ring oscillator in 0.18µm CMOS technology | en_US |
| dc.type | Thesis | en_US |