Comprehensive study of SRAM cell using dual chirality of CNTFET
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Date
2017-07
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
Noise tolerant, low power and fast SRAM cells are of high interest today. Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today’s high performance microprocessors. Rising “nanodevices” promise the possibility of increased integration density. Recently, Carbon Nanotubes (CNTs) have caught the attentions with promising future to replace silicon-based materials due to its superior electrical properties and characteristics. In this work comparison of distinct SRAM cell topologies have been presented. HSPICE has been used for simulations of SRAMs in 32 nm, 180 nm CMOS technology nodes and CNTFET. Different SRAM cell topologies are characterized for data stability, write voltage margin, write delay, write trip voltage, write trip current, write power and static current noise margin. The CNTFET SRAM cell has been concluded to have better performance in terms of Stability, write delay, static current noise margin and the overall performance in terms of SPR has been observed better for CNTFET SRAM cell.
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