Design of hybrid style full adder for low power and high speed application in 0.18μm CMOS technology
| dc.contributor.advisor | Tomar, Abhishek | |
| dc.contributor.author | Adhikari, Shivam | |
| dc.date.accessioned | 2019-01-23T05:15:59Z | |
| dc.date.available | 2019-01-23T05:15:59Z | |
| dc.date.issued | 2018-07 | |
| dc.description.abstract | In the latest digital logic designs, the major challenge is power consumption. In current high speed processors, large amount of power is dissipated in the datapath. Researchers are trying to reduce this power consumption from more than a decade. By using effective topology for logic implementation and transistor count, this problem can be reduced significantly. In the present proposed work a new 18-transistor adder cell has been proposed and implemented in hybrid logic style. The proposed adder cell is compared with previous reported conventional and hybrid adder cells in 0.18μm CMOS technology and parameters like delay, average power consumption and power delay product are compared. The simulation is performed using cadence electronic design automation (EDA) tool. Power delay product of proposed adder is 1.84fJ has been obtained which is smaller than the previous proposed conventional and hybrid adders. The result shows 30% improvement in power delay product in the proposed adder. The reduction in power delay product is due to high speed XOR-XNOR circuit and small propagation path for sum and carry. The proposed adder cell shows the delay of 66.4ps, which is lesser than the previous adders. The proposed adder shows the improvement and provides a solution for the high speed digital circuits. | en_US |
| dc.identifier.uri | http://krishikosh.egranth.ac.in/handle/1/5810092063 | |
| dc.keywords | adder, power requirement, high speed operation, automation | en_US |
| dc.language.iso | en | en_US |
| dc.pages | 64 | en_US |
| dc.publisher | G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand) | en_US |
| dc.research.problem | Automation | en_US |
| dc.sub | Electronics and Communication Engineering | en_US |
| dc.subject | null | en_US |
| dc.theme | Power Consumption | en_US |
| dc.these.type | M.Tech. | |
| dc.title | Design of hybrid style full adder for low power and high speed application in 0.18μm CMOS technology | en_US |
| dc.type | Thesis | en_US |