Design of low power high resolution time-to-digital converter in 45 nm CMOS technology
| dc.contributor.advisor | Tomar, Abhishek | |
| dc.contributor.author | Gurmail Singh | |
| dc.date.accessioned | 2019-05-09T05:14:37Z | |
| dc.date.available | 2019-05-09T05:14:37Z | |
| dc.date.issued | 2019-01 | |
| dc.description.abstract | Increase in the speed of processor demands peripheral devices that can simultaneously operate at high speed while consuming very little power. Power consumption can be reduced by decreasing the effective capacitance at the high impedance nodes of the circuit along with reduction in the number of transistors. Proposed time-to digital converter (TDC) design uses 1024 stages. High number of stages are incorporated to achieve a very good resolution. Circuit is designed by using less number of transistors in order to reduce the power consumption as well as increase the speed of the circuit. Proposed TDC can be used as a phase/frequency detector in Phase Locked-Loop (PLL). In comparison to pseudo differential delay line based TDC and proposed TDC, speed and resolution is improved by more than 19% and 37.5% respectively. PDP has improved. HSPICE tool using 45nm CMOS technology is used for simulation | en_US |
| dc.identifier.uri | http://krishikosh.egranth.ac.in/handle/1/5810102551 | |
| dc.keywords | power requirement, resolution, digital technology, converters | en_US |
| dc.language.iso | en | en_US |
| dc.pages | 58 | en_US |
| dc.publisher | G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand) | en_US |
| dc.research.problem | Converters | en_US |
| dc.sub | Electronics and Communication Engineering | en_US |
| dc.subject | null | en_US |
| dc.theme | Digital Technology | en_US |
| dc.these.type | M.Tech. | en_US |
| dc.title | Design of low power high resolution time-to-digital converter in 45 nm CMOS technology | en_US |
| dc.type | Thesis | en_US |