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Design of high frequency quadrature output ring oscillator in 0.18 µm CMOS process
(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Bohra, Meenu; Tomar, Abhishek
Oscillation frequency, frequency tuning, phase noise and power dissipation are the important parameters in designing any ring VCO with the contemporary sub-micron technologies. The oscillation frequency, frequency tuning, phase noise and power dissipation are still not up to the mark so that ring oscillator can be used in RF application. Various designs had been developed by using effective topologies for reducing power dissipation and phase noise and improving oscillation frequency and frequency tuning. In this thesis, a novel design of ring VCO has been proposed and implemented in TSMC 0.18 µm CMOS technology. The proposed novel design is compared with the earlier proposed designs in 0.18 µm CMOS technology for oscillation frequency, frequency tuning, phase noise and power dissipation. The simulation is done using Cadence EDA tool. The simulated results shows phase noise of the proposed ring VCO equal to -102.9 dBc/Hz at a frequency offset of 1 MHz from a center frequency of 2.61 GHz. The measured power dissipation of the circuit is 25.27 mW. The tuning range of the proposed ring VCO is from 2.61 GHz to 0.2 GHz for a tuning voltage from 0 V to 1.2 V. The layout is drawn and post layout simulation is done which verifies the pre layout results.