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Subject: Electrical Engineering × Author: Kala, Peeyush × End date: 2017 × Start date: 2017 × Type: Thesis ×
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    ThesisItemOpen Access
    Design, development and analysis of a new multilevel inverter topology using GSA based selective harmonic elimination technique
    (G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-08) Kala, Peeyush; Arora, Sudha
    Power electronics finds its major role in the control and conversion of large amount of electric power. In many applications, conversion of dc power to ac power is often required which is achieved with the help of power inverters. Multilevel inverters are the class of inverters which are extensively being used in medium voltage and high power applications owing to their numerous advantages over conventional two-level power inverters. In the current global energy scenario, more emphasis is being given to harness energy from the renewable energy resources such as solar, wind, small hydro, geothermal, bio fuels, ocean energy etc. owing to rapid depletion of conventional energy resources, sharp rise in global energy demand and fuel prices, and growing environmental concerns. Hence, there is a lot of thrust to perform exhaustive research in MLIs for standalone or grid interfaced renewable energy applications. In this thesis work, topological and modulation scheme based solution have been proposed for distributed renewable energy systems such as PV systems, wind energy conversion systems, fuel cells etc., and for battery storage energy systems. As a topological solution, three new MLI topologies have been proposed. The first novel symmetric MLI topology consists of reduced number of switching devices and drivers as compared to various competent MLI topologies. This proposed topology has been implemented in experimental set-up for nine-level configuration. The second MLI topology is an asymmetric reduced switch count topology which is proposed for 31 level configuration. The third proposed MLI topology is 31-level asymmetric inverter topology which is intended for applications where purely resistive load is available. These proposed topologies have been compared with other popular MLI topologies in terms of number of switches, number of sources and number of components. The simulations of all of these proposed MLI topologies have been performed in MATLAB/Simulink environment. Experimental results of proposed symmetric nine-level inverter topology are also presented for the validation of the simulation results. As a modulation scheme based solution, GSA based SHE technique has been implemented in proposed symmetric nine-level inverter which showed the effectiveness of this switching scheme in achieving the objectives of SHE problem.