Performance evaluation of current mirror circuits using CNTFET
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Date
2017-07
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
The current very large scale integration technology based on planar bulk MOSFETs has approached the scaling limits, particularly for analog applications, due to many challenges such as higher leakage, degradation in device matching characteristics, and less gate control over the saturation current. A promising candidate which avoids these difficulties and allows further scaling down is the carbon nano tube field effect transistor (CNTFET). Current mirror is the main building block of analog circuit designing which is used to copy the input current to many current sources. It maintains the output current constant regardless of loading. An ideal current mirror has zero input resistance and infinite output resistance. Current mirror can be used for current amplification, biasing, level shifting and active loading. In this thesis, different existing current mirror circuits have been studied and their performance has been evaluated using CNTFET. All these circuits have been simulated with
the help of HSPICE simulator. 32nm CMOS technology is used for MOSFET based current mirrors and Stanford University CNTFET model is used for CNTFET based current mirrors. Simulation results of MOSFET based current mirrors are then compared with the standard results and simulation results of CNTFET based current mirrors. Parameters considered for the comparison are % error, input/output resistance, input voltage drop, bandwidth and power consumption. With the help of simulation results it is observed that CNTFET improves the % error, output impedance and bandwidth of most of the current mirrors.
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