Design and implementation of high performance hybrid full adders using XOR-XNOR in 90nm CMOS technology
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Date
2020-12
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G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand)
Abstract
The demand for high computational power of processor and dependency on portable application is constantly growing day by day. In the processor thirty percent of power is consumed by the data path. Arithmetic unit is a critical component of this data path. In arithmetic unit, adder plays a vital role not only for addition but also in multiplier, comparator, error detection and correction etc. Many techniques and topologies have been proposed by various authors in the quest of improved performance of adder in terms of power consumption, lesser propagation delay, full voltage swing at the internal and external nodes, and a smaller number of internal nodes. Hybrid logic style is used for implementing the full adder circuit in this thesis. In the hybrid logic style, appropriate logic style is chosen to realize the different modules of the full adder. In this work, at first a XOR-XNOR module is implemented using the complementary pass transistor logic (CPL) and restorer circuit with 10 number of transistors. Furthermore, using this proposed XOR-XNOR design four new full adders are implemented. The proposed work is simulated using the cadence software tool. The proposed XOR-XNOR design showed 7.5% improvement in the power delay product (PDP). The proposed full adder design showed 2 to 28.13 % improvement in PDP. Inaddition
proposed full adder circuits are compared with different reviewed designs in varying supply voltage, process corner and loading conditions. Among the proposed four full adder designs, Design-4 showed best performance. The results of the virtual fabrication of the proposed XOR-XNOR design and Design-4 of full adder circuit are presented and discussed in the present work. The proposed full adder is appropriate for usage in different everyday used electronic applications, for example, in memory and processor-based devices.