“Design and Performance Analysis of an Advanced High Performance Bus Arbiter for System on Chip”
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Date
2018
Authors
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Journal ISSN
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Publisher
MPUAT, Udaipur
Abstract
Most of the FPGA features communicate with each other through bus. Each block is
designed for a specific bus. The buses related to this work is the AMBA bus. It works with the
master / slave architecture. The AMBA bus is extensively utilized in the system on chip solution
for interaction with different peripheral. The proposed work includes the regular AMBA
specifications of (1) burst transfer, (2) several bus masters, (3) single clock edge transition and
(4) split transaction. The proposed design involves the features of the AHB (Advanced Highperformance
Bus) bus like single clock edge transition, split transactions , bus masters and burst
transfer. The proposed arbiter design uses the round robin arbitration algorithm. The AHB
(Advanced High-performance Bus) can be used in the different application in which high
performance and speed are required. Any embedded project which involves in ARM(Advanced
RISC Machine) processors must always make use of this AHB as the common bus throughout
the whole project. It is more advanced and efficient in comparision to the other architectures.
The data transfer is accomplished by a single bus master at a while. Despite the fact that the
arbitration protocol is settled, any arbitration algorithm, for example, fair access or highest
priority can be actualized relying upon the application necessities. VHDL code is utilized to
develop the design and it is synthesized on Virtex-2 series
Description
Design and Performance Analysis of an Advanced High Performance Bus Arbiter for System on Chip
Keywords
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Citation
Sheikh, T. and Joshi, S.