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ThesisItem Open Access Design of high frequency quadrature output ring oscillator in 0.18 µm CMOS process(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Bohra, Meenu; Tomar, AbhishekOscillation frequency, frequency tuning, phase noise and power dissipation are the important parameters in designing any ring VCO with the contemporary sub-micron technologies. The oscillation frequency, frequency tuning, phase noise and power dissipation are still not up to the mark so that ring oscillator can be used in RF application. Various designs had been developed by using effective topologies for reducing power dissipation and phase noise and improving oscillation frequency and frequency tuning. In this thesis, a novel design of ring VCO has been proposed and implemented in TSMC 0.18 µm CMOS technology. The proposed novel design is compared with the earlier proposed designs in 0.18 µm CMOS technology for oscillation frequency, frequency tuning, phase noise and power dissipation. The simulation is done using Cadence EDA tool. The simulated results shows phase noise of the proposed ring VCO equal to -102.9 dBc/Hz at a frequency offset of 1 MHz from a center frequency of 2.61 GHz. The measured power dissipation of the circuit is 25.27 mW. The tuning range of the proposed ring VCO is from 2.61 GHz to 0.2 GHz for a tuning voltage from 0 V to 1.2 V. The layout is drawn and post layout simulation is done which verifies the pre layout results.ThesisItem Open Access Design of 2-6 GHz Flat Gain CMOS LNA for WiMAX applications(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Varshney, Swati; Tomar, AbhishekRadio Frequency signal transmission via wireless technologies is becoming a major method of communication in modern age. But the signal obtained after reception is often corrupted with noise. So, to suppress noise the received signal need to be processed. LNA plays an important role in determining the receiver performance because it is used to amplify the very small signal coming from antenna while adding as little noise and distortion as possible. The main focus of this thesis is to design a Low Noise Amplifier having flat gain for the frequency range of 2-6 GHz. A novel architecture of current reuse LNA with resistive feedback and inductive source degeneration is proposed. Current reuse structure is used to reduce the power consumption and resistive feedback along with inductive source degeneration topology is used for input matching. The input and output matching is better for maximum signal transfer. 0.18 µm TSMC CMOS technology is used for designing the proposed LNA and cadence virtuoso software is used to simulate the schematic of LNA. Simulation shows that the proposed LNA has achieved flat gain, better input & output matching, good isolation and better stability. Amplifier has 15.4 dB gain with 0.3 dB variation, input return loss less than 12.4 dB, output return loss less than -17.4 dB, reverse isolation less than -48.33 dB and noise figure less than 5.2 dB. It exhibit 1-dB compression point -21.86 dBm and third order input intercept point-9.93 dBm at 4 GHz frequency respectively. The circuit draws 21.95 mW from 1.8 V supply voltage.ThesisItem Open Access A compact tri-band microstrip patch antenna for WLAN and Wi-Max applications(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-03) Singh, Namrata; Gangwar, R.P.S.ThesisItem Open Access Comprehensive study of SRAM cell using dual chirality of CNTFET(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Arya, Rashmi; Sharma, K.K.Noise tolerant, low power and fast SRAM cells are of high interest today. Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today’s high performance microprocessors. Rising “nanodevices” promise the possibility of increased integration density. Recently, Carbon Nanotubes (CNTs) have caught the attentions with promising future to replace silicon-based materials due to its superior electrical properties and characteristics. In this work comparison of distinct SRAM cell topologies have been presented. HSPICE has been used for simulations of SRAMs in 32 nm, 180 nm CMOS technology nodes and CNTFET. Different SRAM cell topologies are characterized for data stability, write voltage margin, write delay, write trip voltage, write trip current, write power and static current noise margin. The CNTFET SRAM cell has been concluded to have better performance in terms of Stability, write delay, static current noise margin and the overall performance in terms of SPR has been observed better for CNTFET SRAM cell.ThesisItem Open Access Comprehensive study of CNTFET based positive feedback differential amplifier(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Joshi, Preeti; Sharma, K.K.Regular Feature Size scaling down in today’s CMOS technologies has led to the supply voltage reduction in order to cut short the level of consumed power while maintaining the device reliability that is by preventing gate oxide breakage. In highly scaled processes variations in device parameters increases, which makes CMOS poor performer. The promising new transistor Carbon Nanotube avoids most of the limitations for MOSFET with its ballistic transport and ultra-long mean free path that make it suitable to work at sub-micron regime. These devices due to their small dimensions, shows large variations in their behaviour. In this Study, various parameters differential amplifiers at 32nm are evaluated using CMOS and CNTFET technology and a comparison has been drawn between them for different circuits of differential amplifier and it has been found that CMOS Positive Feedback Differential amplifier gives highest gain and large Bandwidth which get further improved when CNTFET is used for CMOS thus improving the performance of the circuit.ThesisItem Open Access Performance evaluation of current mirror circuits using CNTFET(G.B. Pant University of Agriculture and Technology, Pantnagar - 263145 (Uttarakhand), 2017-07) Tomar, Anjali; Sharma, K.K.The current very large scale integration technology based on planar bulk MOSFETs has approached the scaling limits, particularly for analog applications, due to many challenges such as higher leakage, degradation in device matching characteristics, and less gate control over the saturation current. A promising candidate which avoids these difficulties and allows further scaling down is the carbon nano tube field effect transistor (CNTFET). Current mirror is the main building block of analog circuit designing which is used to copy the input current to many current sources. It maintains the output current constant regardless of loading. An ideal current mirror has zero input resistance and infinite output resistance. Current mirror can be used for current amplification, biasing, level shifting and active loading. In this thesis, different existing current mirror circuits have been studied and their performance has been evaluated using CNTFET. All these circuits have been simulated with the help of HSPICE simulator. 32nm CMOS technology is used for MOSFET based current mirrors and Stanford University CNTFET model is used for CNTFET based current mirrors. Simulation results of MOSFET based current mirrors are then compared with the standard results and simulation results of CNTFET based current mirrors. Parameters considered for the comparison are % error, input/output resistance, input voltage drop, bandwidth and power consumption. With the help of simulation results it is observed that CNTFET improves the % error, output impedance and bandwidth of most of the current mirrors.